1. Technical Field
This invention relates to the field of dynamic computing and, more particularly, to a chaotic computing architecture for logic gates.
2. Description of the Related Art
Conventional computing systems rely upon timed operations and Boolean algebra to perform calculations. That is, the flow and processing of signals within conventional computing systems is under the control and coordination of a timing source such as a signal from a system clock. With the passing of each clock cycle, signals can be processed, typically using various combinations of logic gates to implement one or more Boolean algebraic functions.
Conventional computing systems also are static in nature and lack a flexible computing architecture. Within static computing systems, the various hardware components of the computing system cannot be reconnected or reconfigured during operation. For example, the functionality of hardware components such as logic gates cannot be changed once the component is fabricated. Moreover, once a plurality of components or logic gates are organized to form a data processing system or particular Boolean function, the components become fixed in circuitry. This is the case whether the function is implemented as a series of discrete components or on a silicon chip. In either case, the structure of the resulting circuit cannot be reconfigured or reordered into a different design.
Some computing modules, however, can be reconfigured to a limited degree. For example, field programmable gate arrays provide a limited degree of flexibility with respect to reconfiguration. One class of FPGA, referred to as a one-time configurable architecture, can be programmed one time by using fuses and antifuses as switches to make or break circuit connections. Another class of FPGA, referred to as a multi-time configurable architecture, can be adjusted to implement different architecture configurations each time the device is used.
Still another class of FPGA allows for hardware to evolve during the course of operation of a design. Such FPGA's are referred to as having dynamic architectures, and more specifically as having dynamic rewire architectures. For example, conventional dynamic FPGA's can include uncommitted logic cells and routing resources whose functions and interconnections are determined by user-defined configuration data stored in static random access memory (RAM). The static RAM can be modified at run-time, thereby allowing the configuration for some part of the chip to be altered while other circuits operate without interruption. Other embodiments include microcontrollers which allow for rerouting of data within the FPGA.
In any case, while the present state of electronic design has begun to develop dynamic computing architectures, such efforts have been limited to simply redirecting signal flows or “rewiring” devices or components such as FPGA's.